1. Field of the Invention
The present invention relates to a power switching circuit for a CMOS LSI.
2. Description of the Related Art
In recent years, a so-called system-on-chip technology of integrating all the elements in a chip formed a main stream in LSI technologies. Accordingly, a plurality of functional blocks exist on a chip and thus it is necessary to allow the respective functional blocks to operated with the minimum voltage and to deactivate the power sources of some functional blocks at the time of non-use, for the purpose of avoiding interference of noise in the respective functional blocks and reducing power consumption.
Accordingly, power source separation that a power source is divided and supplied to the functional blocks is now used for any LSI. However, the power source separation causes increase in the number of terminals in the LSI. Accordingly, it is often difficult to supply power to all the functional blocks in a specific process such as LSI shipping inspection.
As countermeasures, it can be considered that power switches connecting the power sources separated for each functional block are mounted on the chip only in such a specific case such as LSI shipping inspection. An example of such a power switch mounted on the chip is an analog switch.
For example, a circuit configuration of an analog switching circuit in which an excessive current is suppressed from flowing to elements from input terminals under a specific use condition is disclosed in Japanese Unexamined Patent Application Publication No. 2003-229748 (see FIG. 3 ). FIG. 18 is a schematic diagram illustrating an example of such a configuration that the analog switch disclosed in Japanese Unexamined Patent Application Publication No. 2003-229749 (see FIG. 3 ) serves as a power switch.
The gate potentials of MOS transistors P1 and N14 which are connected in parallel to each other and which have different polarities are controlled by nodes PG and NG. When the switch is in the ON state and the potential of a first power source VDD1 is higher than that of a second power source VDD2, the voltage of the first power source VDD1 is delivered from a terminal AIN to a terminal AOUT. When the potential of the second power source VDD2 is higher than that of the first power source VDD1, the voltage of the second power source VDD2 is delivered from the terminal AOUT to the terminal AIN.
At this time, since the higher voltage of the voltages of the first power source VDD1 and the second power source VDD2 is selected as the well potential of the P-type transistor P1 by a well-potential control circuit 2a and is supplied from an output terminal VNW of the well-potential control circuit 2a, an excessive current does not flow through the P-type transistor P1, whether the voltage of the first power source VDD1 is higher than that of the second power source VDD2.
A circuit configuration which can prevent an unnecessary current from flowing through a parasitic diode to the earth potential from an input terminal in an analog switch under a specific use condition is disclosed in Patent Document 2.
FIG. 19 is a schematic diagram illustrating an example of such a configuration that the analog switch disclosed in Japanese Unexamined Patent Application Publication No. 10-41800 (see FIG. 1) serves as a power switch. The gate potentials of MOS transistors P1 and N14 which are connected in parallel and which have different polarities are controlled by nodes PG and NG and a voltage equal to the well potential of the P-type transistor P1 is supplied to a power source of a gate control circuit 1g. 
When the switch is in the ON state and the potential of a second power source VDD2 is higher than the potential of a first power source VDD1, the potential of the second power source VDD2 is delivered from a terminal AOUT to a terminal AIN. In this case, since the voltage subsequently equal to the potential of the second power source VDD2 is supplied as the well potential of the P-type transistor from the second power source VDD2 through a diode D1, excessive current flows through the well of the P-type transistor P1.
However, in the conventional analog switches, when the switches are turned off, a problem is which voltage of a plurality of power sources is used as the voltage of a control signal for controlling the switches. Specifically, in order to turn off the P-type transistor constituting the analog switch, it is necessary to use the highest voltage of the source voltages as the gate voltage of the P-type transistor.
Specifically speaking, it is necessary to turn off the switches between the power sources of the functional blocks at the time of normal use of an LSI, but when a difference is generated between the source voltages of the functional blocks and the voltage of the control signal of the analog switch connecting the power sources of the functional blocks is lower than another source voltage, the gate voltage of the P-type transistor constituting the analog switch may be lower than the source voltage or the drain voltage thereof. In this case, there is a problem that the P-type transistor is not turned off and thus current flows between the different power sources connected to each other through the analog switch.
Accordingly, it is required that the gate voltage of the P-type transistor constituting the analog switch is the highest voltage of the power sources of the functional blocks between with the switch is connected.
In the method of supplying the highest voltage among the voltages of the power sources of the functional blocks to the gate control circuit by the use of a diode, since voltage drop occurs in the diode element, the high-level output from the gate control circuit drops in voltage, thereby sufficiently turning off the P-type transistor constituting the analog switch. Accordingly, there is a problem that leakage of current occurs.